The present invention relates in general to semiconductor devices and, more particularly, to vertical MOS power transistors.
Switching regulators achieve a high efficiency by using a transistor to switch current through an inductor or transformer to generate a regulated output voltage. One type of switching transistor often used in switching regulators is a power double diffused metal-oxide-semiconductor (DMOS) transistor. A DMOS transistor typically is a vertical transistor in which current flows laterally through a plurality of electrically parallel channels formed along the top surface of a semiconductor die to a common drain, and then vertically through the drain to a drain electrode formed at the bottom surface of the die.
Existing DMOS transistors have the drawback of a high drain to gate capacitance, which Slows down the switching and reduces the efficiency of the transistor and/or system. As a result, the switching regulators have a low efficiency and the transistor has a high heat dissipation and reduced reliability. In order to achieve a small die size and low cost, the gate electrode is formed over a thin dielectric layer and routed over portions of the common drain that lie at the top surface. The overlap of the gate electrode and common drain generates a substantial portion of the overall drain to gate capacitance and results in a reduction in the switching speed and frequency response of the switching power transistor.
Hence, there is a need for a power transistor that has a low drain to gate capacitance in order to switch at a higher speed to reduce power dissipation and increase reliability.